VMS/VAX Lecture Notes

Intro

VAX - Virtual Address Extension

VMS - Virtual Memory System

Mixed Workload

• Timesharing, real-time, batch, all kinds of applications.
• H/W range is wide, can work on both high-end workstation and low-end desktop.
  • Minimum resources
  • No dedicated paging disk (Some systems have all paging done in a special high performance disk)

Address Space

32-bit virtual address space.

21-bit virtual page number and 9-bit byte offset within the page. Thus each page is $2^9 = 512$ bytes.

  0 +---------------+
    |       P0      |
    +---------------+
    |       P1      |
2^31+---------------+
    |      SYS      |
    +---------------+
    |               |
2^32+---------------+

P0 has user program, and grows toward higher addresses.

P1 stores the process-specific data, as well as the program image for the command interpreter, which grows toward lower addresses.

Each region is defined by a page table, and each page table is defined by two hardware registers: a base address register and a length register.

The page table for system space, called the system page table, is located by reference to the system page table base register, which contains its physical address. System page table is in physical memory, and not pageable. It can take care of recursive error.

The P0 and P1 page tables for each process are located in the system-space section of the address space; therefore, the P0 and P1 page table base registers contain virtual address. The P0 and P1 page tables can themselves be paged because they are in virtual memory. The translation of the process-space virtual address involves two accesses: one to the system page table, and one to the process page table.

The VAX-11 hardware provides a translation buffer for caching virtual-to-physical translations.

The P0 and P1 page tables are process specific, the corresponding base and length registers are changed by a process context switch.

Sys Call

The first few pages of system space, called the vector region, contain pointers to executive service routines in system space. Users call service routines as they would call any user-written procedure.

The OS is protected through the memory management system, which uses a hardware access mode mechanism; executive code and data are not made accessible to programs executing in the least privileged (user) mode.

Implementation

Page table is implemented as an array. The reason that a sparse table is not used is that the page table may grow too big, but not fully used.

Local replacement

Choose a page to page out from a local resident set, rather than a global set, as in normal LRU cache selection.

Page caching

When paged out from resident set, may go to free list of modify-list, depending on whether it is dirty and thus needs to be written back to disk. Here, the page has a 2nd chance to get back into the resident set. Page caching is implemented as FIFO.

Clustering

• Amortized I/O ~100 pages / IO operation
• Clustered R/W
• Ext3